1. Field of the Invention
The present invention relates generally to a circuit for correcting a reproduced signal and particularly to a reproduced signal correcting circuit for correcting a time base error of a video signal reproduced from a video tape recorder (VTR) and for compensating for its dropouts. More particularly but not exclusively, this invention relates to an apparatus in which a time base error correcting memory is also used as a dropout compensating memory for carrying out the above-described correction and compensation of the reproduced signal.
2. Description of the Prior Art
Generally in the prior art VTR, a time base error corrector (TBC) and a frame synchronizer are used to directly process a reproduced signal that is played back one after another from a magnetic tape. In this case, a dropout of the reproduced signal is compensated for by a dropout compensating circuit which is provided at the stage prior to the TBC, the frame synchronizer and the like. Such circuit arrangement is generally formed as shown in FIG. 1. This circuit arrangement is disclosed in greater detail in, for example, U.S. Pat. No. 4,165,524. This prior art circuit arrangement will hereinafter be described below briefly.
As shown in FIG. 1, a recorded signal played back from a magnetic tape 1 by a magnetic head 2 is supplied to and processed by a reproducing circuit 3 and then converted to a digital signal by an analog-to-digital (A/D) converting circuit 4 as a reproduced digital signal RD. This digital signal RD is supplied to a dropout compensating circuit 5.
The dropout compensating circuit 5 comprises a dropout compensating memory 6 which receives the reproduced digital signal RD and a switching circuit 7 which is changed in position by a dropout detecting signal DO. The switching circuit 7 is changed in position by the dropout detecting signal DO that is independently detected by a detecting circuit (not shown) when the dropout occurs in the reproduced digital signal RD to thereby supply the output of the dropout compensating memory 6 to a time base error correcting circuit 8, whereas when no dropout occurs in the reproduced digital signal RD, the switching circuit 7 allows the reproduced digital signal RD to be supplied to the time base error correcting circuit 8 directly.
The dropout compensating circuit 5 operates such that as to the picture element having a dropout occurred, it is replaced with sampling signal of its one line or two lines before or with an average value of the sampling signals corresponding to the lines before and after the picture element having the dropout whereby the picture element having the dropout is compensated for. Accordingly, when the dropout occurs in the reproduced digital signal RD, such picture element can be compensated for by utilizing the correlation between the lines.
Further, in the time base error correcting circuit 8, a digital signal DOD obtained from the dropout compensating circuit 5 is received by its main memory 11. On the basis of a write signal WS obtained from a write/read control circuit 12, the main memory 11 stores at its predetermined address a sample data that is supplied thereto at every line. The data thus written in the main memory 11 is read out therefrom at a predetermined cycle on the basis of a read signal RS obtained from the write/read control circuit 12. This read-out data is supplied to and converted to an analog signal by a digital-to-analog (D/A) converting circuit 13 and then delivered therefrom as a reproduced output PBO. Thus, the reproduced output PBO is transmitted as the signal in which the jitter component thereof is corrected on the basis of the digital signal DOD in the cycle of the read signal RS.
As described above, in the prior art circuit arrangement shown in FIG. 1, the main memory 11 with the memory capacity available for at least ten and several lines must be provided and the dropout compensating memory 6 with the memory capacity of 1H (H is the horizontal period) or 2H must be provided so as to compensate for the dropout.
If the two memories 6 and 11 are provided independently from each other as mentioned above, the capacity of memory is increased on the whole of the circuit arrangement. In addition, the control circuits for independently operating the respective memories must be provided. Accordingly, this puts a limit on making the whole circuit arrangement small in size.